An Effective VHDL Implementation of IEEE 754 Floating Point Unit using CLA and Rad-4 Modified Booth Encoder Multiplier

Most of the signal processing algorithms using floating point arithmetic, which requires millions of operations per second to be performed. For such stringent requirement design of fast, precise and efficient circuit is needed. This article present an IEEE 754 floating point unit using carry look ahead adder and radix-4 modified Booth encoder multiplier algorithm and the design is compared in terms of speed , area and power consumption. The adder used here will increase the speed and the multiplier is used to reduce power consumption, area and number of partial product get generated. The floating point unit design deals with the detection of exceptions and trapped overflow and underflow exceptions as an integral part of the rounding unit. This work is used to reduce area, power consumption and speed up the operations with more accurate results. The basic methodology and approach are implemented in VHDL (Very Large Scale Integration Hardware Description Language). Keywords-FP multiplier, MBE.